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| Start | Days | Course | City | State | Register |
| --- | --- | --- | --- | --- | --- |
| 06/02/2026 | 3 | Accelerating Applications with the Vitis Unified Software Environment ( [AI-ACCEL](/content/trainingpdf/AI-ACCEL.pdf)) | Orono (Minneapolis) | MN | Full |
| 06/02/2026 | 3 | Accelerating Applications with the Vitis Unified Software Environment ( [AI-ACCEL](/content/trainingpdf/AI-ACCEL.pdf)) | Online | Online | Full |
| 06/02/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Orono (Minneapolis) | MN | Closed |
| 06/02/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Online | Online | Closed |
| 06/02/2026 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( [FPGA-STAXDCADV](/content/trainingpdf/FPGA-STAXDCADV.pdf)) | Orono (Minneapolis) | MN | Full |
| 06/02/2026 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( [FPGA-STAXDCADV](/content/trainingpdf/FPGA-STAXDCADV.pdf)) | Online | Online | Full |
| 06/04/2026 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 ( [AIE-ARCH](/content/trainingpdf/AIE-ARCH.pdf)) | Schaumburg | IL | Closed |
| 06/04/2026 | 2 | Zynq UltraScale+ MPSoC for the Hardware Designer ( [EMBD-ZUPHW](/content/trainingpdf/EMBD-ZUPHW.pdf)) | Schaumburg | IL | Closed |
| 06/04/2026 | 2 | Designing with the UltraScale and UltraScale+ Architectures ( [FPGA-US](/content/trainingpdf/FPGA-US.pdf)) | Schaumburg | IL | Closed |
| 06/04/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 1 ( [FPGA-VDES1](/content/trainingpdf/FPGA-VDES1.pdf)) | Orono (Minneapolis) | MN | Closed |
| 06/04/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 1 ( [FPGA-VDES1](/content/trainingpdf/FPGA-VDES1.pdf)) | Online | Online | Closed |
| 06/04/2026 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( [SOM-ROBOTICS](/content/trainingpdf/SOM-ROBOTICS.pdf)) | Orono (Minneapolis) | MN | Closed |
| 06/04/2026 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( [SOM-ROBOTICS](/content/trainingpdf/SOM-ROBOTICS.pdf)) | Online | Online | Closed |
| 06/05/2026 | 1 | Designing with Versal AI Engine DSP Applications ( [AIE-DSP](/content/trainingpdf/AIE-DSP.pdf)) | Orono (Minneapolis) | MN | Full |
| 06/05/2026 | 1 | Designing with Versal AI Engine DSP Applications ( [AIE-DSP](/content/trainingpdf/AIE-DSP.pdf)) | Online | Online | Full |
| 06/05/2026 | 1 | Migrating to the Vitis Unified IDE ( [EMBD-VITIS](/content/trainingpdf/EMBD-VITIS.pdf)) | Orono (Minneapolis) | MN | Closed |
| 06/05/2026 | 1 | Migrating to the Vitis Unified IDE ( [EMBD-VITIS](/content/trainingpdf/EMBD-VITIS.pdf)) | Online | Online | Closed |
| 06/08/2026 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( [AIE-GRAPH](/content/trainingpdf/AIE-GRAPH.pdf)) | Orono (Minneapolis) | MN | Full |
| 06/08/2026 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( [AIE-GRAPH](/content/trainingpdf/AIE-GRAPH.pdf)) | Online | Online | Full |
| 06/08/2026 | 2 | Design Closure Techniques ( [FPGA-DSGNCLOSURE](/content/trainingpdf/FPGA-DSGNCLOSURE.pdf)) | Orono (Minneapolis) | MN | Closed |
| 06/08/2026 | 2 | Design Closure Techniques ( [FPGA-DSGNCLOSURE](/content/trainingpdf/FPGA-DSGNCLOSURE.pdf)) | Online | Online | Closed |
| 06/08/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Orono (Minneapolis) | MN | Closed |
| 06/08/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Online | Online | Closed |
| 06/09/2026 | 4 | Xilinx Rapid Development Embedded Design ( [EMBD-88080](/content/trainingpdf/EMBD-88080.pdf)) | Orono (Minneapolis) | MN | Full |
| 06/09/2026 | 4 | Xilinx Rapid Development Embedded Design ( [EMBD-88080](/content/trainingpdf/EMBD-88080.pdf)) | Online | Online | Full |
| 06/10/2026 | 1 | Designing with Versal AI Engine Quick Start ( [AIE-QSTART](/content/trainingpdf/AIE-QSTART.pdf)) | Olathe | KS | Full |
| 06/11/2026 | 2 | Designing with Versal AI Engine Kernel Programming and Optimization - 3 ( [AIE-KERNEL](/content/trainingpdf/AIE-KERNEL.pdf)) | Cedar Rapids | IA | [Register](/content/training/register/?date=06-11-2026&class=AIE-KERNEL&loc=CedarRapidsIA/index.html) |
| 06/11/2026 | 2 | Developing Multimedia Solutions Using a Hardened VCU-VDU ( [EMBD-MMEDIA](/content/trainingpdf/EMBD-MMEDIA.pdf)) | Cedar Rapids | IA | [Register](/content/training/register/?date=06-11-2026&class=EMBD-MMEDIA&loc=CedarRapidsIA/index.html) |
| 06/11/2026 | 2 | Designing with the IP Integrator Tool ( [FPGA-IPI](/content/trainingpdf/FPGA-IPI.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=06-11-2026&class=FPGA-IPI&loc=OronoMN/index.html) |
| 06/11/2026 | 2 | Designing with the IP Integrator Tool ( [FPGA-IPI](/content/trainingpdf/FPGA-IPI.pdf)) | Online | Online | [Register](/content/training/register/?date=06-11-2026&class=FPGA-IPI&loc=Online/index.html) |
| 06/11/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 3 ( [FPGA-VDES3](/content/trainingpdf/FPGA-VDES3.pdf)) | Chicago | IL | [Register](/content/training/register/?date=06-11-2026&class=FPGA-VDES3&loc=ChicagoIL/index.html) |
| 06/15/2026 | 3 | Operating Systems and Hypervisors in Adaptive SoCs ( [SOC-OS-HYPER](/content/trainingpdf/SOC-OS-HYPER.pdf)) | Chicago | IL | [Register](/content/training/register/?date=06-15-2026&class=SOC-OS-HYPER&loc=ChicagoIL/index.html) |
| 06/15/2026 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( [SOM-ROBOTICS](/content/trainingpdf/SOM-ROBOTICS.pdf)) | Online | Online | [Register](/content/training/register/?date=06-15-2026&class=SOM-ROBOTICS&loc=Online/index.html) |
| 06/15/2026 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( [SOM-ROBOTICS](/content/trainingpdf/SOM-ROBOTICS.pdf)) | Naperville | IL | [Register](/content/training/register/?date=06-15-2026&class=SOM-ROBOTICS&loc=NapervilleIL/index.html) |
| 06/15/2026 | 1 | Designing with the Versal Adaptive SoC Serial Transceivers ( [VER-TRX](/content/trainingpdf/VER-TRX.pdf)) | Chicago | IL | [Register](/content/training/register/?date=06-15-2026&class=VER-TRX&loc=ChicagoIL/index.html) |
| 06/17/2026 | 2 | Vitis Model Composer A MATLAB and Simulink-based Product ( [DSP-MCSIM](/content/trainingpdf/DSP-MCSIM.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=06-17-2026&class=DSP-MCSIM&loc=OronoMN/index.html) |
| 06/17/2026 | 2 | Vitis Model Composer A MATLAB and Simulink-based Product ( [DSP-MCSIM](/content/trainingpdf/DSP-MCSIM.pdf)) | Online | Online | [Register](/content/training/register/?date=06-17-2026&class=DSP-MCSIM&loc=Online/index.html) |
| 06/17/2026 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( [FPGA-DFX](/content/trainingpdf/FPGA-DFX.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=06-17-2026&class=FPGA-DFX&loc=OronoMN/index.html) |
| 06/17/2026 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( [FPGA-DFX](/content/trainingpdf/FPGA-DFX.pdf)) | Online | Online | [Register](/content/training/register/?date=06-17-2026&class=FPGA-DFX&loc=Online/index.html) |
| 06/17/2026 | 3 | Designing with Verilog ( [LANG-VERILOG](/content/trainingpdf/LANG-VERILOG.pdf)) | Overland Park | KS | [Register](/content/training/register/?date=06-17-2026&class=LANG-VERILOG&loc=OverlandParkKS/index.html) |
| 06/17/2026 | 1 | Designing with the Versal Adaptive SoC Quick Start ( [VER-QSTART](/content/trainingpdf/VER-QSTART.pdf)) | Fargo | ND | [Register](/content/training/register/?date=06-17-2026&class=VER-QSTART&loc=FargoND/index.html) |
| 06/22/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 1 ( [FPGA-VDES1](/content/trainingpdf/FPGA-VDES1.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=06-22-2026&class=FPGA-VDES1&loc=OronoMN/index.html) |
| 06/22/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 1 ( [FPGA-VDES1](/content/trainingpdf/FPGA-VDES1.pdf)) | Online | Online | [Register](/content/training/register/?date=06-22-2026&class=FPGA-VDES1&loc=Online/index.html) |
| 06/22/2026 | 2 | Zynq UltraScale+ MPSoC Boot and Platform Management ( [MPSOC-BOOT-PM](/content/trainingpdf/MPSOC-BOOT-PM.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=06-22-2026&class=MPSOC-BOOT-PM&loc=OronoMN/index.html) |
| 06/22/2026 | 2 | Zynq UltraScale+ MPSoC Boot and Platform Management ( [MPSOC-BOOT-PM](/content/trainingpdf/MPSOC-BOOT-PM.pdf)) | Online | Online | [Register](/content/training/register/?date=06-22-2026&class=MPSOC-BOOT-PM&loc=Online/index.html) |
| 06/24/2026 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( [FPGA-STAXDCADV](/content/trainingpdf/FPGA-STAXDCADV.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=06-24-2026&class=FPGA-STAXDCADV&loc=OronoMN/index.html) |
| 06/24/2026 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( [FPGA-STAXDCADV](/content/trainingpdf/FPGA-STAXDCADV.pdf)) | Online | Online | [Register](/content/training/register/?date=06-24-2026&class=FPGA-STAXDCADV&loc=Online/index.html) |
| 06/24/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=06-24-2026&class=FPGA-VDES2&loc=OronoMN/index.html) |
| 06/24/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Online | Online | [Register](/content/training/register/?date=06-24-2026&class=FPGA-VDES2&loc=Online/index.html) |
| 06/24/2026 | 3 | Designing with VHDL ( [LANG-VHDL](/content/trainingpdf/LANG-VHDL.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=06-24-2026&class=LANG-VHDL&loc=OronoMN/index.html) |
| 06/24/2026 | 3 | Designing with VHDL ( [LANG-VHDL](/content/trainingpdf/LANG-VHDL.pdf)) | Online | Online | [Register](/content/training/register/?date=06-24-2026&class=LANG-VHDL&loc=Online/index.html) |
| 06/25/2026 | 2 | Embedded Heterogeneous Design ( [EMBD-HET](/content/trainingpdf/EMBD-HET.pdf)) | Schaumburg | IL | [Register](/content/training/register/?date=06-25-2026&class=EMBD-HET&loc=SchaumburgIL/index.html) |
| 06/30/2026 | 2 | Adaptive SoCs for System Architects ( [ASOC-SA](/content/trainingpdf/ASOC-SA.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=06-30-2026&class=ASOC-SA&loc=OronoMN/index.html) |
| 06/30/2026 | 2 | Adaptive SoCs for System Architects ( [ASOC-SA](/content/trainingpdf/ASOC-SA.pdf)) | Online | Online | [Register](/content/training/register/?date=06-30-2026&class=ASOC-SA&loc=Online/index.html) |
| 06/30/2026 | 2 | Using Vision-based Applications with the Kria KV260 Vision AI ( [SOM-VISION](/content/trainingpdf/SOM-VISION.pdf)) | Schaumburg | IL | [Register](/content/training/register/?date=06-30-2026&class=SOM-VISION&loc=SchaumburgIL/index.html) |
| 06/30/2026 | 1 | Designing with the Versal Adaptive SoC Serial Transceivers ( [VER-TRX](/content/trainingpdf/VER-TRX.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=06-30-2026&class=VER-TRX&loc=OronoMN/index.html) |
| 06/30/2026 | 1 | Designing with the Versal Adaptive SoC Serial Transceivers ( [VER-TRX](/content/trainingpdf/VER-TRX.pdf)) | Online | Online | [Register](/content/training/register/?date=06-30-2026&class=VER-TRX&loc=Online/index.html) |
| 07/02/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 4 ( [FPGA-VDES4](/content/trainingpdf/FPGA-VDES4.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-02-2026&class=FPGA-VDES4&loc=OronoMN/index.html) |
| 07/02/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 4 ( [FPGA-VDES4](/content/trainingpdf/FPGA-VDES4.pdf)) | Online | Online | [Register](/content/training/register/?date=07-02-2026&class=FPGA-VDES4&loc=Online/index.html) |
| 07/03/2026 | 1 | Designing with Versal AI Engine Quick Start ( [AIE-QSTART](/content/trainingpdf/AIE-QSTART.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-03-2026&class=AIE-QSTART&loc=OronoMN/index.html) |
| 07/03/2026 | 1 | Designing with Versal AI Engine Quick Start ( [AIE-QSTART](/content/trainingpdf/AIE-QSTART.pdf)) | Online | Online | [Register](/content/training/register/?date=07-03-2026&class=AIE-QSTART&loc=Online/index.html) |
| 07/06/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Overland Park | KS | [Register](/content/training/register/?date=07-06-2026&class=CONN-RFSOC&loc=OverlandParkKS/index.html) |
| 07/06/2026 | 2 | Zynq SoC System Architecture ( [EMBD-ZSA](/content/trainingpdf/EMBD-ZSA.pdf)) | Overland Park | KS | [Register](/content/training/register/?date=07-06-2026&class=EMBD-ZSA&loc=OverlandParkKS/index.html) |
| 07/06/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 1 ( [FPGA-VDES1](/content/trainingpdf/FPGA-VDES1.pdf)) | Overland Park | KS | [Register](/content/training/register/?date=07-06-2026&class=FPGA-VDES1&loc=OverlandParkKS/index.html) |
| 07/06/2026 | 2 | Advanced VHDL ( [LANG-ADVVHDL](/content/trainingpdf/LANG-ADVVHDL.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-06-2026&class=LANG-ADVVHDL&loc=OronoMN/index.html) |
| 07/06/2026 | 2 | Advanced VHDL ( [LANG-ADVVHDL](/content/trainingpdf/LANG-ADVVHDL.pdf)) | Online | Online | [Register](/content/training/register/?date=07-06-2026&class=LANG-ADVVHDL&loc=Online/index.html) |
| 07/06/2026 | 2 | Designing with the Versal Adaptive SoC Memory Interfaces ( [VER-MEM](/content/trainingpdf/VER-MEM.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-06-2026&class=VER-MEM&loc=OronoMN/index.html) |
| 07/06/2026 | 2 | Designing with the Versal Adaptive SoC Memory Interfaces ( [VER-MEM](/content/trainingpdf/VER-MEM.pdf)) | Online | Online | [Register](/content/training/register/?date=07-06-2026&class=VER-MEM&loc=Online/index.html) |
| 07/06/2026 | 2 | Designing with the Versal Adaptive SoC Power and Board Design ( [VER-MEM](/content/trainingpdf/VER-MEM.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-06-2026&class=VER-PWR-BD&loc=OronoMN/index.html) |
| 07/06/2026 | 2 | Designing with the Versal Adaptive SoC Power and Board Design ( [VER-PWR-BD](/content/trainingpdf/VER-PWR-BD.pdf)) | Online | Online | [Register](/content/training/register/?date=07-06-2026&class=VER-PWR-BD&loc=Online/index.html) |
| 07/08/2026 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( [AIE-GRAPH](/content/trainingpdf/AIE-GRAPH.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-08-2026&class=AIE-GRAPH&loc=OronoMN/index.html) |
| 07/08/2026 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( [AIE-GRAPH](/content/trainingpdf/AIE-GRAPH.pdf)) | Online | Online | [Register](/content/training/register/?date=07-08-2026&class=AIE-GRAPH&loc=Online/index.html) |
| 07/08/2026 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( [FPGA-DFX](/content/trainingpdf/FPGA-DFX.pdf)) | Schaumburg | IL | [Register](/content/training/register/?date=07-08-2026&class=FPGA-DFX&loc=SchaumburgIL/index.html) |
| 07/08/2026 | 3 | Designing with Verilog ( [LANG-VERILOG](/content/trainingpdf/LANG-VERILOG.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-08-2026&class=LANG-VERILOG&loc=OronoMN/index.html) |
| 07/08/2026 | 3 | Designing with Verilog ( [LANG-VERILOG](/content/trainingpdf/LANG-VERILOG.pdf)) | Online | Online | [Register](/content/training/register/?date=07-08-2026&class=LANG-VERILOG&loc=Online/index.html) |
| 07/09/2026 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( [FPGA-DFX](/content/trainingpdf/FPGA-DFX.pdf)) | Overland Park | KS | [Register](/content/training/register/?date=07-09-2026&class=FPGA-DFX&loc=OverlandParkKS/index.html) |
| 07/09/2026 | 2 | Designing with the Versal Adaptive SoC PCI Express Systems ( [VER-PCIE](/content/trainingpdf/VER-PCIE.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-09-2026&class=VER-PCIE&loc=OronoMN/index.html) |
| 07/09/2026 | 2 | Designing with the Versal Adaptive SoC PCI Express Systems ( [VER-PCIE](/content/trainingpdf/VER-PCIE.pdf)) | Online | Online | [Register](/content/training/register/?date=07-09-2026&class=VER-PCIE&loc=Online/index.html) |
| 07/13/2026 | 2 | Designing with Versal AI Engine Kernel Programming and Optimization - 3 ( [AIE-KERNEL](/content/trainingpdf/AIE-KERNEL.pdf)) | Online | Online | [Register](/content/training/register/?date=07-13-2026&class=AIE-KERNEL&loc=Online/index.html) |
| 07/13/2026 | 2 | Designing with Versal AI Engine Kernel Programming and Optimization - 3 ( [AIE-KERNEL](/content/trainingpdf/AIE-KERNEL.pdf)) | Fargo | ND | [Register](/content/training/register/?date=07-13-2026&class=AIE-KERNEL&loc=FargoND/index.html) |
| 07/13/2026 | 2 | Developing AI Inference Solutions with the Vitis AI Platform ( [AI-INFER](/content/trainingpdf/AI-INFER.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-13-2026&class=AI-INFER&loc=OronoMN/index.html) |
| 07/13/2026 | 2 | Developing AI Inference Solutions with the Vitis AI Platform ( [AI-INFER](/content/trainingpdf/AI-INFER.pdf)) | Online | Online | [Register](/content/training/register/?date=07-13-2026&class=AI-INFER&loc=Online/index.html) |
| 07/13/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Naperville | IL | [Register](/content/training/register/?date=07-13-2026&class=CONN-RFSOC&loc=NapervilleIL/index.html) |
| 07/13/2026 | 2 | Embedded Systems Design ( [EMBD-HW](/content/trainingpdf/EMBD-HW.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-13-2026&class=EMBD-HW&loc=OronoMN/index.html) |
| 07/13/2026 | 2 | Embedded Systems Design ( [EMBD-HW](/content/trainingpdf/EMBD-HW.pdf)) | Online | Online | [Register](/content/training/register/?date=07-13-2026&class=EMBD-HW&loc=Online/index.html) |
| 07/13/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Overland Park | KS | [Register](/content/training/register/?date=07-13-2026&class=FPGA-VDES2&loc=OverlandParkKS/index.html) |
| 07/13/2026 | 3 | Designing with the Versal Adaptive SoC Design Methodology ( [VER-DM](/content/trainingpdf/VER-DM.pdf)) | Hoffman Estates | IL | [Register](/content/training/register/?date=07-13-2026&class=VER-DM&loc=HoffmanIL/index.html) |
| 07/14/2026 | 4 | Xilinx Rapid Development Embedded Design ( [EMBD-88080](/content/trainingpdf/EMBD-88080.pdf)) | Online | Online | [Register](/content/training/register/?date=07-14-2026&class=EMBD-88080&loc=Online/index.html) |
| 07/14/2026 | 4 | Xilinx Rapid Development Embedded Design ( [EMBD-88080](/content/trainingpdf/EMBD-88080.pdf)) | Olathe | KS | [Register](/content/training/register/?date=07-14-2026&class=EMBD-88080&loc=OlatheKS/index.html) |
| 07/15/2026 | 3 | Accelerating Applications with the Vitis Unified Software Environment ( [AI-ACCEL](/content/trainingpdf/AI-ACCEL.pdf)) | Chicago | IL | [Register](/content/training/register/?date=07-15-2026&class=AI-ACCEL&loc=ChicagoIL/index.html) |
| 07/15/2026 | 2 | Designing an Integrated PCI Express System ( [CONN-PCIE](/content/trainingpdf/CONN-PCIE.pdf)) | Chicago | IL | [Register](/content/training/register/?date=07-15-2026&class=CONN-PCIE&loc=ChicagoIL/index.html) |
| 07/15/2026 | 2 | High-Level Synthesis with the Vitis Unified IDE ( [DSP-HLS](/content/trainingpdf/DSP-HLS.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-15-2026&class=DSP-HLS&loc=OronoMN/index.html) |
| 07/15/2026 | 2 | High-Level Synthesis with the Vitis Unified IDE ( [DSP-HLS](/content/trainingpdf/DSP-HLS.pdf)) | Online | Online | [Register](/content/training/register/?date=07-15-2026&class=DSP-HLS&loc=Online/index.html) |
| 07/15/2026 | 3 | Embedded Systems Software Design ( [EMBD-SW](/content/trainingpdf/EMBD-SW.pdf)) | Schaumburg | IL | [Register](/content/training/register/?date=07-15-2026&class=EMBD-SW&loc=SchaumburgIL/index.html) |
| 07/15/2026 | 2 | Designing with the Versal Adaptive SoC Architecture ( [VER-ARCH](/content/trainingpdf/VER-ARCH.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-15-2026&class=VER-ARCH&loc=OronoMN/index.html) |
| 07/15/2026 | 2 | Designing with the Versal Adaptive SoC Architecture ( [VER-ARCH](/content/trainingpdf/VER-ARCH.pdf)) | Online | Online | [Register](/content/training/register/?date=07-15-2026&class=VER-ARCH&loc=Online/index.html) |
| 07/16/2026 | 2 | UltraFast Design Methodology ( [FPGA-VDM](/content/trainingpdf/FPGA-VDM.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-16-2026&class=FPGA-VDM&loc=OronoMN/index.html) |
| 07/16/2026 | 2 | UltraFast Design Methodology ( [FPGA-VDM](/content/trainingpdf/FPGA-VDM.pdf)) | Online | Online | [Register](/content/training/register/?date=07-16-2026&class=FPGA-VDM&loc=Online/index.html) |
| 07/16/2026 | 2 | Verification with SystemVerilog ( [LANG-SVVER](/content/trainingpdf/LANG-SVVER.pdf)) | Schaumburg | IL | [Register](/content/training/register/?date=07-16-2026&class=LANG-SVVER&loc=SchaumburgIL/index.html) |
| 07/20/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-20-2026&class=CONN-RFSOC&loc=OronoMN/index.html) |
| 07/20/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Online | Online | [Register](/content/training/register/?date=07-20-2026&class=CONN-RFSOC&loc=Online/index.html) |
| 07/20/2026 | 2 | Zynq UltraScale+ MPSoC for the Hardware Designer ( [EMBD-ZUPHW](/content/trainingpdf/EMBD-ZUPHW.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-20-2026&class=EMBD-ZUPHW&loc=OronoMN/index.html) |
| 07/20/2026 | 2 | Zynq UltraScale+ MPSoC for the Hardware Designer ( [EMBD-ZUPHW](/content/trainingpdf/EMBD-ZUPHW.pdf)) | Online | Online | [Register](/content/training/register/?date=07-20-2026&class=EMBD-ZUPHW&loc=Online/index.html) |
| 07/20/2026 | 2 | Designing with the Versal Adaptive SoC Architecture ( [VER-ARCH](/content/trainingpdf/VER-ARCH.pdf)) | Schaumburg | IL | [Register](/content/training/register/?date=07-20-2026&class=VER-ARCH&loc=SchaumburgIL/index.html) |
| 07/20/2026 | 1 | Designing with the Versal Adaptive SoC Network on Chip ( [VER-NOC](/content/trainingpdf/VER-NOC.pdf)) | Naperville | IL | [Register](/content/training/register/?date=07-20-2026&class=VER-NOC&loc=NapervilleIL/index.html) |
| 07/20/2026 | 2 | Designing with the Versal Adaptive SoC Power and Board Design ( [VER-PWR-BD](/content/trainingpdf/VER-PWR-BD.pdf)) | Naperville | IL | [Register](/content/training/register/?date=07-20-2026&class=VER-PWR-BD&loc=NapervilleIL/index.html) |
| 07/21/2026 | 3 | Designing with VHDL ( [LANG-VHDL](/content/trainingpdf/LANG-VHDL.pdf)) | Online | Online | [Register](/content/training/register/?date=07-21-2026&class=LANG-VHDL&loc=Online/index.html) |
| 07/21/2026 | 3 | Designing with VHDL ( [LANG-VHDL](/content/trainingpdf/LANG-VHDL.pdf)) | Olathe | KS | [Register](/content/training/register/?date=07-21-2026&class=LANG-VHDL&loc=OlatheKS/index.html) |
| 07/22/2026 | 3 | Accelerating Applications with the Vitis Unified Software Environment ( [AI-ACCEL](/content/trainingpdf/AI-ACCEL.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-22-2026&class=AI-ACCEL&loc=OronoMN/index.html) |
| 07/22/2026 | 3 | Accelerating Applications with the Vitis Unified Software Environment ( [AI-ACCEL](/content/trainingpdf/AI-ACCEL.pdf)) | Online | Online | [Register](/content/training/register/?date=07-22-2026&class=AI-ACCEL&loc=Online/index.html) |
| 07/22/2026 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( [FPGA-STAXDCADV](/content/trainingpdf/FPGA-STAXDCADV.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-22-2026&class=FPGA-STAXDCADV&loc=OronoMN/index.html) |
| 07/22/2026 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( [FPGA-STAXDCADV](/content/trainingpdf/FPGA-STAXDCADV.pdf)) | Online | Online | [Register](/content/training/register/?date=07-22-2026&class=FPGA-STAXDCADV&loc=Online/index.html) |
| 07/23/2026 | 2 | Zynq UltraScale+ MPSoC for the System Architect ( [EMBD-ZUPSA](/content/trainingpdf/EMBD-ZUPSA.pdf)) | Champaign-Urbana | IL | [Register](/content/training/register/?date=07-23-2026&class=EMBD-ZUPSA&loc=ChampaignIL/index.html) |
| 07/23/2026 | 2 | Design Closure Techniques ( [FPGA-DSGNCLOSURE](/content/trainingpdf/FPGA-DSGNCLOSURE.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-23-2026&class=FPGA-DSGNCLOSURE&loc=OronoMN/index.html) |
| 07/23/2026 | 2 | Design Closure Techniques ( [FPGA-DSGNCLOSURE](/content/trainingpdf/FPGA-DSGNCLOSURE.pdf)) | Online | Online | [Register](/content/training/register/?date=07-23-2026&class=FPGA-DSGNCLOSURE&loc=Online/index.html) |
| 07/23/2026 | 2 | Designing with the IP Integrator Tool ( [FPGA-IPI](/content/trainingpdf/FPGA-IPI.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-23-2026&class=FPGA-IPI&loc=OronoMN/index.html) |
| 07/23/2026 | 2 | Designing with the IP Integrator Tool ( [FPGA-IPI](/content/trainingpdf/FPGA-IPI.pdf)) | Online | Online | [Register](/content/training/register/?date=07-23-2026&class=FPGA-IPI&loc=Online/index.html) |
| 07/23/2026 | 2 | Designing with SystemVerilog ( [LANG-SVDES](/content/trainingpdf/LANG-SVDES.pdf)) | Olathe | KS | [Register](/content/training/register/?date=07-23-2026&class=LANG-SVDES&loc=OlatheKS/index.html) |
| 07/23/2026 | 2 | Designing with the Versal Adaptive SoC Power and Board Design ( [VER-PWR-BD](/content/trainingpdf/VER-PWR-BD.pdf)) | Champaign-Urbana | IL | [Register](/content/training/register/?date=07-23-2026&class=VER-PWR-BD&loc=ChampaignIL/index.html) |
| 07/27/2026 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 ( [AIE-ARCH](/content/trainingpdf/AIE-ARCH.pdf)) | Online | Online | [Register](/content/training/register/?date=07-27-2026&class=AIE-ARCH&loc=Online/index.html) |
| 07/27/2026 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 ( [AIE-ARCH](/content/trainingpdf/AIE-ARCH.pdf)) | Fargo | ND | [Register](/content/training/register/?date=07-27-2026&class=AIE-ARCH&loc=FargoND/index.html) |
| 07/27/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Naperville | IL | [Register](/content/training/register/?date=07-27-2026&class=CONN-RFSOC&loc=NapervilleIL/index.html) |
| 07/27/2026 | 2 | High-Level Synthesis with the Vitis Unified IDE ( [DSP-HLS](/content/trainingpdf/DSP-HLS.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-27-2026&class=DSP-HLS&loc=OronoMN/index.html) |
| 07/27/2026 | 2 | High-Level Synthesis with the Vitis Unified IDE ( [DSP-HLS](/content/trainingpdf/DSP-HLS.pdf)) | Online | Online | [Register](/content/training/register/?date=07-27-2026&class=DSP-HLS&loc=Online/index.html) |
| 07/27/2026 | 2 | Embedded Heterogeneous Design ( [EMBD-HET](/content/trainingpdf/EMBD-HET.pdf)) | Olathe | KS | [Register](/content/training/register/?date=07-27-2026&class=EMBD-HET&loc=OlatheKS/index.html) |
| 07/27/2026 | 1 | Designing with the Versal Adaptive SoC Network on Chip ( [VER-NOC](/content/trainingpdf/VER-NOC.pdf)) | Saint Louis | MO | [Register](/content/training/register/?date=07-27-2026&class=VER-NOC&loc=SaintLouisMO/index.html) |
| 07/27/2026 | 2 | Designing with the Versal Adaptive SoC PCI Express Systems ( [VER-PCIE](/content/trainingpdf/VER-PCIE.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-27-2026&class=VER-PCIE&loc=OronoMN/index.html) |
| 07/27/2026 | 2 | Designing with the Versal Adaptive SoC PCI Express Systems ( [VER-PCIE](/content/trainingpdf/VER-PCIE.pdf)) | Online | Online | [Register](/content/training/register/?date=07-27-2026&class=VER-PCIE&loc=Online/index.html) |
| 07/28/2026 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( [AIE-GRAPH](/content/trainingpdf/AIE-GRAPH.pdf)) | Fargo | ND | [Register](/content/training/register/?date=07-28-2026&class=AIE-GRAPH&loc=FargoND/index.html) |
| 07/29/2026 | 2 | Adaptive SoCs for System Architects ( [ASOC-SA](/content/trainingpdf/ASOC-SA.pdf)) | Overland Park | KS | [Register](/content/training/register/?date=07-29-2026&class=ASOC-SA&loc=OverlandParkKS/index.html) |
| 07/29/2026 | 2 | Vitis Model Composer A MATLAB and Simulink-based Product ( [DSP-MCSIM](/content/trainingpdf/DSP-MCSIM.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-29-2026&class=DSP-MCSIM&loc=OronoMN/index.html) |
| 07/29/2026 | 2 | Vitis Model Composer A MATLAB and Simulink-based Product ( [DSP-MCSIM](/content/trainingpdf/DSP-MCSIM.pdf)) | Online | Online | [Register](/content/training/register/?date=07-29-2026&class=DSP-MCSIM&loc=Online/index.html) |
| 07/29/2026 | 3 | Designing with the Versal Adaptive SoC Design Methodology ( [VER-DM](/content/trainingpdf/VER-DM.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=07-29-2026&class=VER-DM&loc=OronoMN/index.html) |
| 07/29/2026 | 3 | Designing with the Versal Adaptive SoC Design Methodology ( [VER-DM](/content/trainingpdf/VER-DM.pdf)) | Online | Online | [Register](/content/training/register/?date=07-29-2026&class=VER-DM&loc=Online/index.html) |
| 07/30/2026 | 2 | Zynq UltraScale+ MPSoC for the Software Developer ( [EMBD-ZUPSW](/content/trainingpdf/EMBD-ZUPSW.pdf)) | Olathe | KS | [Register](/content/training/register/?date=07-30-2026&class=EMBD-ZUPSW&loc=OlatheKS/index.html) |
| 07/30/2026 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( [FPGA-DFX](/content/trainingpdf/FPGA-DFX.pdf)) | Naperville | IL | [Register](/content/training/register/?date=07-30-2026&class=FPGA-DFX&loc=NapervilleIL/index.html) |
| 08/03/2026 | 2 | Developing Multimedia Solutions Using a Hardened VCU-VDU ( [EMBD-MMEDIA](/content/trainingpdf/EMBD-MMEDIA.pdf)) | Overland Park | KS | [Register](/content/training/register/?date=08-03-2026&class=EMBD-MMEDIA&loc=OverlandParkKS/index.html) |
| 08/03/2026 | 3 | Embedded Systems Software Design ( [EMBD-SW](/content/trainingpdf/EMBD-SW.pdf)) | Olathe | KS | [Register](/content/training/register/?date=08-03-2026&class=EMBD-SW&loc=OlatheKS/index.html) |
| 08/05/2026 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( [FPGA-STAXDCADV](/content/trainingpdf/FPGA-STAXDCADV.pdf)) | Schaumburg | IL | [Register](/content/training/register/?date=08-05-2026&class=FPGA-STAXDCADV&loc=SchaumburgIL/index.html) |
| 08/05/2026 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( [FPGA-STAXDCADV](/content/trainingpdf/FPGA-STAXDCADV.pdf)) | Online | Online | [Register](/content/training/register/?date=08-05-2026&class=FPGA-STAXDCADV&loc=Online/index.html) |
| 08/06/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 1 ( [FPGA-VDES1](/content/trainingpdf/FPGA-VDES1.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-06-2026&class=FPGA-VDES1&loc=OronoMN/index.html) |
| 08/06/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 1 ( [FPGA-VDES1](/content/trainingpdf/FPGA-VDES1.pdf)) | Online | Online | [Register](/content/training/register/?date=08-06-2026&class=FPGA-VDES1&loc=Online/index.html) |
| 08/12/2026 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 ( [AIE-ARCH](/content/trainingpdf/AIE-ARCH.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-12-2026&class=AIE-ARCH&loc=OronoMN/index.html) |
| 08/12/2026 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 ( [AIE-ARCH](/content/trainingpdf/AIE-ARCH.pdf)) | Online | Online | [Register](/content/training/register/?date=08-12-2026&class=AIE-ARCH&loc=Online/index.html) |
| 08/12/2026 | 3 | Designing with Verilog ( [LANG-VERILOG](/content/trainingpdf/LANG-VERILOG.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-12-2026&class=LANG-VERILOG&loc=OronoMN/index.html) |
| 08/12/2026 | 3 | Designing with Verilog ( [LANG-VERILOG](/content/trainingpdf/LANG-VERILOG.pdf)) | Online | Online | [Register](/content/training/register/?date=08-12-2026&class=LANG-VERILOG&loc=Online/index.html) |
| 08/12/2026 | 2 | Zynq UltraScale+ MPSoC Boot and Platform Management ( [MPSOC-BOOT-PM](/content/trainingpdf/MPSOC-BOOT-PM.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-12-2026&class=MPSOC-BOOT-PM&loc=OronoMN/index.html) |
| 08/12/2026 | 2 | Zynq UltraScale+ MPSoC Boot and Platform Management ( [MPSOC-BOOT-PM](/content/trainingpdf/MPSOC-BOOT-PM.pdf)) | Online | Online | [Register](/content/training/register/?date=08-12-2026&class=MPSOC-BOOT-PM&loc=Online/index.html) |
| 08/13/2026 | 2 | Developing AI Inference Solutions with the Vitis AI Platform ( [AI-INFER](/content/trainingpdf/AI-INFER.pdf)) | Chicago | IL | [Register](/content/training/register/?date=08-13-2026&class=AI-INFER&loc=ChicagoIL/index.html) |
| 08/13/2026 | 2 | Designing an Integrated PCI Express System ( [CONN-PCIE](/content/trainingpdf/CONN-PCIE.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-13-2026&class=CONN-PCIE&loc=OronoMN/index.html) |
| 08/13/2026 | 2 | Designing an Integrated PCI Express System ( [CONN-PCIE](/content/trainingpdf/CONN-PCIE.pdf)) | Online | Online | [Register](/content/training/register/?date=08-13-2026&class=CONN-PCIE&loc=Online/index.html) |
| 08/13/2026 | 2 | Zynq SoC System Architecture ( [EMBD-ZSA](/content/trainingpdf/EMBD-ZSA.pdf)) | Chicago | IL | [Register](/content/training/register/?date=08-13-2026&class=EMBD-ZSA&loc=ChicagoIL/index.html) |
| 08/13/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-13-2026&class=FPGA-VDES2&loc=OronoMN/index.html) |
| 08/13/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Online | Online | [Register](/content/training/register/?date=08-13-2026&class=FPGA-VDES2&loc=Online/index.html) |
| 08/17/2026 | 2 | Embedded Design with PetaLinux Tools ( [EMBD-PLNX](/content/trainingpdf/EMBD-PLNX.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-17-2026&class=EMBD-PLNX&loc=OronoMN/index.html) |
| 08/17/2026 | 2 | Embedded Design with PetaLinux Tools ( [EMBD-PLNX](/content/trainingpdf/EMBD-PLNX.pdf)) | Online | Online | [Register](/content/training/register/?date=08-17-2026&class=EMBD-PLNX&loc=Online/index.html) |
| 08/17/2026 | 1 | Designing with the Versal Adaptive SoC Hardware Debug ( [VER-DEBUG](/content/trainingpdf/VER-DEBUG.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-17-2026&class=VER-DEBUG&loc=OronoMN/index.html) |
| 08/17/2026 | 1 | Designing with the Versal Adaptive SoC Hardware Debug ( [VER-DEBUG](/content/trainingpdf/VER-DEBUG.pdf)) | Online | Online | [Register](/content/training/register/?date=08-17-2026&class=VER-DEBUG&loc=Online/index.html) |
| 08/17/2026 | 2 | Designing with the Versal Adaptive SoC Power and Board Design ( [VER-PWR-BD](/content/trainingpdf/VER-PWR-BD.pdf)) | Online | Online | [Register](/content/training/register/?date=08-17-2026&class=VER-PWR-BD&loc=Online/index.html) |
| 08/17/2026 | 2 | Designing with the Versal Adaptive SoC Power and Board Design ( [VER-PWR-BD](/content/trainingpdf/VER-PWR-BD.pdf)) | Fargo | ND | [Register](/content/training/register/?date=08-17-2026&class=VER-PWR-BD&loc=FargoND/index.html) |
| 08/18/2026 | 3 | Accelerating Applications with the Vitis Unified Software Environment ( [AI-ACCEL](/content/trainingpdf/AI-ACCEL.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-18-2026&class=AI-ACCEL&loc=OronoMN/index.html) |
| 08/18/2026 | 3 | Accelerating Applications with the Vitis Unified Software Environment ( [AI-ACCEL](/content/trainingpdf/AI-ACCEL.pdf)) | Online | Online | [Register](/content/training/register/?date=08-18-2026&class=AI-ACCEL&loc=Online/index.html) |
| 08/18/2026 | 4 | Xilinx Rapid Development Embedded Design ( [EMBD-88080](/content/trainingpdf/EMBD-88080.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-18-2026&class=EMBD-88080&loc=OronoMN/index.html) |
| 08/18/2026 | 4 | Xilinx Rapid Development Embedded Design ( [EMBD-88080](/content/trainingpdf/EMBD-88080.pdf)) | Online | Online | [Register](/content/training/register/?date=08-18-2026&class=EMBD-88080&loc=Online/index.html) |
| 08/18/2026 | 2 | UltraFast Design Methodology ( [FPGA-VDM](/content/trainingpdf/FPGA-VDM.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-18-2026&class=FPGA-VDM&loc=OronoMN/index.html) |
| 08/18/2026 | 2 | UltraFast Design Methodology ( [FPGA-VDM](/content/trainingpdf/FPGA-VDM.pdf)) | Online | Online | [Register](/content/training/register/?date=08-18-2026&class=FPGA-VDM&loc=Online/index.html) |
| 08/18/2026 | 1 | Designing with the Versal Adaptive SoC Network on Chip ( [VER-NOC](/content/trainingpdf/VER-NOC.pdf)) | Saint Louis | MO | [Register](/content/training/register/?date=08-18-2026&class=VER-NOC&loc=SaintLouisMO/index.html) |
| 08/19/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-19-2026&class=CONN-RFSOC&loc=OronoMN/index.html) |
| 08/19/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Online | Online | [Register](/content/training/register/?date=08-19-2026&class=CONN-RFSOC&loc=Online/index.html) |
| 08/19/2026 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( [FPGA-DFX](/content/trainingpdf/FPGA-DFX.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-19-2026&class=FPGA-DFX&loc=OronoMN/index.html) |
| 08/19/2026 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( [FPGA-DFX](/content/trainingpdf/FPGA-DFX.pdf)) | Online | Online | [Register](/content/training/register/?date=08-19-2026&class=FPGA-DFX&loc=Online/index.html) |
| 08/19/2026 | 3 | Designing with VHDL ( [LANG-VHDL](/content/trainingpdf/LANG-VHDL.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-19-2026&class=LANG-VHDL&loc=OronoMN/index.html) |
| 08/19/2026 | 3 | Designing with VHDL ( [LANG-VHDL](/content/trainingpdf/LANG-VHDL.pdf)) | Online | Online | [Register](/content/training/register/?date=08-19-2026&class=LANG-VHDL&loc=Online/index.html) |
| 08/19/2026 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( [SOM-ROBOTICS](/content/trainingpdf/SOM-ROBOTICS.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-19-2026&class=SOM-ROBOTICS&loc=OronoMN/index.html) |
| 08/19/2026 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( [SOM-ROBOTICS](/content/trainingpdf/SOM-ROBOTICS.pdf)) | Online | Online | [Register](/content/training/register/?date=08-19-2026&class=SOM-ROBOTICS&loc=Online/index.html) |
| 08/20/2026 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( [AIE-GRAPH](/content/trainingpdf/AIE-GRAPH.pdf)) | Fargo | ND | [Register](/content/training/register/?date=08-20-2026&class=AIE-GRAPH&loc=FargoND/index.html) |
| 08/20/2026 | 2 | Design Closure Techniques ( [FPGA-DSGNCLOSURE](/content/trainingpdf/FPGA-DSGNCLOSURE.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-20-2026&class=FPGA-DSGNCLOSURE&loc=OronoMN/index.html) |
| 08/20/2026 | 2 | Design Closure Techniques ( [FPGA-DSGNCLOSURE](/content/trainingpdf/FPGA-DSGNCLOSURE.pdf)) | Online | Online | [Register](/content/training/register/?date=08-20-2026&class=FPGA-DSGNCLOSURE&loc=Online/index.html) |
| 08/20/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-20-2026&class=FPGA-VDES2&loc=OronoMN/index.html) |
| 08/20/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Online | Online | [Register](/content/training/register/?date=08-20-2026&class=FPGA-VDES2&loc=Online/index.html) |
| 08/20/2026 | 2 | Designing with the Versal Adaptive SoC Memory Interfaces ( [VER-MEM](/content/trainingpdf/VER-MEM.pdf)) | Overland Park | KS | [Register](/content/training/register/?date=08-20-2026&class=VER-MEM&loc=OverlandParkKS/index.html) |
| 08/21/2026 | 1 | Designing with Versal AI Engine DSP Applications ( [AIE-DSP](/content/trainingpdf/AIE-DSP.pdf)) | Cedar Rapids | IA | [Register](/content/training/register/?date=08-21-2026&class=AIE-DSP&loc=CedarRapidsIA/index.html) |
| 08/21/2026 | 1 | Migrating to the Vitis Unified IDE ( [EMBD-VITIS](/content/trainingpdf/EMBD-VITIS.pdf)) | Cedar Rapids | IA | [Register](/content/training/register/?date=08-21-2026&class=EMBD-VITIS&loc=CedarRapidsIA/index.html) |
| 08/24/2026 | 2 | Embedded Systems Design ( [EMBD-HW](/content/trainingpdf/EMBD-HW.pdf)) | Online | Online | [Register](/content/training/register/?date=08-24-2026&class=EMBD-HW&loc=Online/index.html) |
| 08/24/2026 | 2 | Embedded Systems Design ( [EMBD-HW](/content/trainingpdf/EMBD-HW.pdf)) | Fargo | ND | [Register](/content/training/register/?date=08-24-2026&class=EMBD-HW&loc=FargoND/index.html) |
| 08/24/2026 | 2 | Zynq UltraScale+ MPSoC for the System Architect ( [EMBD-ZUPSA](/content/trainingpdf/EMBD-ZUPSA.pdf)) | Chicago | IL | [Register](/content/training/register/?date=08-24-2026&class=EMBD-ZUPSA&loc=ChicagoIL/index.html) |
| 08/24/2026 | 2 | Designing with the IP Integrator Tool ( [FPGA-IPI](/content/trainingpdf/FPGA-IPI.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-24-2026&class=FPGA-IPI&loc=OronoMN/index.html) |
| 08/24/2026 | 2 | Designing with the IP Integrator Tool ( [FPGA-IPI](/content/trainingpdf/FPGA-IPI.pdf)) | Online | Online | [Register](/content/training/register/?date=08-24-2026&class=FPGA-IPI&loc=Online/index.html) |
| 08/24/2026 | 2 | Advanced VHDL ( [LANG-ADVVHDL](/content/trainingpdf/LANG-ADVVHDL.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-24-2026&class=LANG-ADVVHDL&loc=OronoMN/index.html) |
| 08/24/2026 | 2 | Advanced VHDL ( [LANG-ADVVHDL](/content/trainingpdf/LANG-ADVVHDL.pdf)) | Online | Online | [Register](/content/training/register/?date=08-24-2026&class=LANG-ADVVHDL&loc=Online/index.html) |
| 08/24/2026 | 1 | Migrating from UltraScale+ Devices to Versal Adaptive SoCs ( [VER-MGRT](/content/trainingpdf/VER-MGRT.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-24-2026&class=VER-MGRT&loc=OronoMN/index.html) |
| 08/24/2026 | 1 | Migrating from UltraScale+ Devices to Versal Adaptive SoCs ( [VER-MGRT](/content/trainingpdf/VER-MGRT.pdf)) | Online | Online | [Register](/content/training/register/?date=08-24-2026&class=VER-MGRT&loc=Online/index.html) |
| 08/24/2026 | 1 | Designing with the Versal Adaptive SoC Network on Chip ( [VER-NOC](/content/trainingpdf/VER-NOC.pdf)) | Naperville | IL | [Register](/content/training/register/?date=08-24-2026&class=VER-NOC&loc=NapervilleIL/index.html) |
| 08/26/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-26-2026&class=CONN-RFSOC&loc=OronoMN/index.html) |
| 08/26/2026 | 3 | Designing with the Zynq UltraScale+ RFSoC ( [CONN-RFSOC](/content/trainingpdf/CONN-RFSOC.pdf)) | Online | Online | [Register](/content/training/register/?date=08-26-2026&class=CONN-RFSOC&loc=Online/index.html) |
| 08/26/2026 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( [FPGA-STAXDCADV](/content/trainingpdf/FPGA-STAXDCADV.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-26-2026&class=FPGA-STAXDCADV&loc=OronoMN/index.html) |
| 08/26/2026 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( [FPGA-STAXDCADV](/content/trainingpdf/FPGA-STAXDCADV.pdf)) | Online | Online | [Register](/content/training/register/?date=08-26-2026&class=FPGA-STAXDCADV&loc=Online/index.html) |
| 08/31/2026 | 3 | Accelerating Applications with the Vitis Unified Software Environment ( [AI-ACCEL](/content/trainingpdf/AI-ACCEL.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-31-2026&class=AI-ACCEL&loc=OronoMN/index.html) |
| 08/31/2026 | 3 | Accelerating Applications with the Vitis Unified Software Environment ( [AI-ACCEL](/content/trainingpdf/AI-ACCEL.pdf)) | Online | Online | [Register](/content/training/register/?date=08-31-2026&class=AI-ACCEL&loc=Online/index.html) |
| 08/31/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Schaumburg | IL | [Register](/content/training/register/?date=08-31-2026&class=FPGA-VDES2&loc=SchaumburgIL/index.html) |
| 08/31/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 2 ( [FPGA-VDES2](/content/trainingpdf/FPGA-VDES2.pdf)) | Online | Online | [Register](/content/training/register/?date=08-31-2026&class=FPGA-VDES2&loc=Online/index.html) |
| 08/31/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 3 ( [FPGA-VDES3](/content/trainingpdf/FPGA-VDES3.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-31-2026&class=FPGA-VDES3&loc=OronoMN/index.html) |
| 08/31/2026 | 2 | Designing FPGAs Using the Vivado Design Suite 3 ( [FPGA-VDES3](/content/trainingpdf/FPGA-VDES3.pdf)) | Online | Online | [Register](/content/training/register/?date=08-31-2026&class=FPGA-VDES3&loc=Online/index.html) |
| 08/31/2026 | 2 | Designing with SystemVerilog ( [LANG-SVDES](/content/trainingpdf/LANG-SVDES.pdf)) | Overland Park | KS | [Register](/content/training/register/?date=08-31-2026&class=LANG-SVDES&loc=OverlandParkKS/index.html) |
| 08/31/2026 | 1 | Designing with the Versal Adaptive SoC Hardware Debug ( [VER-DEBUG](/content/trainingpdf/VER-DEBUG.pdf)) | Saint Louis | MO | [Register](/content/training/register/?date=08-31-2026&class=VER-DEBUG&loc=SaintLouisMO/index.html) |
| 08/31/2026 | 1 | Designing with the Versal Adaptive SoC Quick Start ( [VER-QSTART](/content/trainingpdf/VER-QSTART.pdf)) | Orono (Minneapolis) | MN | [Register](/content/training/register/?date=08-31-2026&class=VER-QSTART&loc=OronoMN/index.html) |
| 08/31/2026 | 1 | Designing with the Versal Adaptive SoC Quick Start ( [VER-QSTART](/content/trainingpdf/VER-QSTART.pdf)) | Online | Online | [Register](/content/training/register/?date=08-31-2026&class=VER-QSTART&loc=Online/index.html) |
| 09/16/2026 | 1 | Getting Started with AMD's Versal Adaptive SoC ( [VERSAL-101](/content/trainingpdf/VERSAL-101.pdf)) | Online | Online | [Register](/content/training/register/?date=09-16-2026&class=VERSAL-101&loc=Online&payment_type=PAYPO&ac=free_webinar/index.html) |

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## Don't see a class?

If you do not see a class that you're interested in on the schedule, please either [give us a call](/content/location/index.html) or [contact us](/content/contact/index.html).  We will work to rearrange the schedule so that key members of your team can get the Xilinx training they need as soon as possible.

## Cancellation Policies

These are our cancellation policies:

### Student Cancellation Policy

- Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
- Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
- Student cancellations must be sent [here](/content/contact/?reason=RegCan/index.html).

### Course Cancellation Policy

- We regret that from time to time classes will need to be rescheduled or cancelled.
- In the event of cancellation, live on-line training may be offered as a substitute.
- Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
- Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
- For additional information or to schedule a private class contact us [here](/content/contact/?reason=PrivateTraining/index.html).

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