### A wide variety of courses on FPGA, MPSoC, and ACAP design Courses may use tools later than indicated in the course descriptions below. The following course descriptions with pricing. If a class you need is not on the schedule, please feel free to [contact us](/content/contact/index.html). Please note that extra fees may apply to update some but not all legacy courses, e.g., ISE courses. Please contact us for details. - AI-ACCEL: [Accelerating Applications with the Vitis Unified Software Environment](/content/trainingpdf/AI-ACCEL.pdf) - AIE-ARCH: [Designing with Versal AI Engine Architecture and Design Flow - 1](/content/trainingpdf/AIE-ARCH.pdf) - AIE-DSP: [Designing with Versal AI Engine DSP Applications](/content/trainingpdf/AIE-DSP.pdf) - AIE-GRAPH: [Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2](/content/trainingpdf/AIE-GRAPH.pdf) - AIE-KERNEL: [Designing with Versal AI Engine Kernel Programming and Optimization - 3](/content/trainingpdf/AIE-KERNEL.pdf) - AIE-MLV2-ARCH: [Designing with Versal AI Edge Series Gen 2 AIE-ML v2 Architecture and Design Flow](/content/trainingpdf/AIE-MLV2-ARCH.pdf) - AIE-QSTART: [Designing with Versal AI Engine Quick Start](/content/trainingpdf/AIE-QSTART.pdf) - AI-INFER: [Developing AI Inference Solutions with the Vitis AI Platform](/content/trainingpdf/AI-INFER.pdf) - ASOC-SA (formerly MPSOC-ACAP-SA): [Adaptive SoCs for System Architects](/content/trainingpdf/ASOC-SA.pdf) - CONN-PCIE: [Designing an Integrated PCI Express System](/content/trainingpdf/CONN-PCIE.pdf) - CONN-RFSOC: [Designing with the Zynq UltraScale+ RFSoC](/content/trainingpdf/CONN-RFSOC.pdf) - DSP-HLS: [High-Level Synthesis with the Vitis Unified IDE](/content/trainingpdf/DSP-HLS.pdf) - DSP-MCSIM: [Vitis Model Composer A MATLAB and Simulink-based Product](/content/trainingpdf/DSP-MCSIM.pdf) - EMBD-88080: [Xilinx Rapid Development Embedded Design](/content/trainingpdf/EMBD-88080.pdf) - EMBD-EDF: [Designing with the AMD Embedded Development Framework (EDF)](/content/trainingpdf/EMBD-EDF.pdf) - EMBD-HET: [Embedded Heterogeneous Design](/content/trainingpdf/EMBD-HET.pdf) - EMBD-HW: [Embedded Systems Design](/content/trainingpdf/EMBD-HW.pdf) - EMBD-MGRT-X861: [Migration from Intel to AMD x86 Embedded Solutions - 1](/content/trainingpdf/EMBD-MGRT-X861.pdf) - EMBD-MMEDIA: [Developing Multimedia Solutions Using a Hardened VCU-VDU](/content/trainingpdf/EMBD-MMEDIA.pdf) - EMBD-PLNX: [Embedded Design with PetaLinux Tools](/content/trainingpdf/EMBD-PLNX.pdf) - EMBD-SW: [Embedded Systems Software Design](/content/trainingpdf/EMBD-SW.pdf) - EMBD-VITIS: [Migrating to the Vitis Unified IDE](/content/trainingpdf/EMBD-VITIS.pdf) - EMBD-YOCTO: [Embedded Linux Development Using Yocto](/content/trainingpdf/EMBD-YOCTO.pdf) - EMBD-ZSA: [Zynq SoC System Architecture](/content/trainingpdf/EMBD-ZSA.pdf) - EMBD-ZUPHW: [Zynq UltraScale+ MPSoC for the Hardware Designer](/content/trainingpdf/EMBD-ZUPHW.pdf) - EMBD-ZUPSA: [Zynq UltraScale+ MPSoC for the System Architect](/content/trainingpdf/EMBD-ZUPSA.pdf) - EMBD-ZUPSW: [Zynq UltraScale+ MPSoC for the Software Developer](/content/trainingpdf/EMBD-ZUPSW.pdf) - FPGA-DFX: [Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite](/content/trainingpdf/FPGA-DFX.pdf) - FPGA-DSGNCLOSURE: [Design Closure Techniques](/content/trainingpdf/FPGA-DSGNCLOSURE.pdf) - FPGA-IPI: [Designing with the IP Integrator Tool](/content/trainingpdf/FPGA-IPI.pdf) - FPGA-STAXDCADV: [Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite](/content/trainingpdf/FPGA-STAXDCADV.pdf) - FPGA-SU-ARCH: [Designing with the Spartan UltraScale+ FPGA Architecture](/content/trainingpdf/FPGA-SU-ARCH.pdf) - FPGA-US: [Designing with the UltraScale and UltraScale+ Architectures](/content/trainingpdf/FPGA-US.pdf) - FPGA-VDES1: [Designing FPGAs Using the Vivado Design Suite 1](/content/trainingpdf/FPGA-VDES1.pdf) - FPGA-VDES2: [Designing FPGAs Using the Vivado Design Suite 2](/content/trainingpdf/FPGA-VDES2.pdf) - FPGA-VDES3: [Designing FPGAs Using the Vivado Design Suite 3](/content/trainingpdf/FPGA-VDES3.pdf) - FPGA-VDES4: [Designing FPGAs Using the Vivado Design Suite 4](/content/trainingpdf/FPGA-VDES4.pdf) - FPGA-VDM: [UltraFast Design Methodology](/content/trainingpdf/FPGA-VDM.pdf) - LANG-ADVVHDL: [Advanced VHDL](/content/trainingpdf/LANG-ADVVHDL.pdf) - LANG-SVDES: [Designing with SystemVerilog](/content/trainingpdf/LANG-SVDES.pdf) - LANG-SVVER: [Verification with SystemVerilog](/content/trainingpdf/LANG-SVVER.pdf) - LANG-VERILOG: [Designing with Verilog](/content/trainingpdf/LANG-VERILOG.pdf) - LANG-VHDL: [Designing with VHDL](/content/trainingpdf/LANG-VHDL.pdf) - MGRT-HIP: [CUDA to HIPROCm Migration](/content/trainingpdf/MGRT-HIP.pdf) - MPSOC-BOOT-PM: [Zynq UltraScale+ MPSoC Boot and Platform Management](/content/trainingpdf/MPSOC-BOOT-PM.pdf) - SOC-OS-HYPER: [Operating Systems and Hypervisors in Adaptive SoCs](/content/trainingpdf/SOC-OS-HYPER.pdf) - SOM-ROBOTICS: [Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS](/content/trainingpdf/SOM-ROBOTICS.pdf) - SOM-VISION: [Using Vision-based Applications with the Kria KV260 Vision AI](/content/trainingpdf/SOM-VISION.pdf) - VER2-ARCH: [Designing with the Versal AI Edge Series Gen 2 and Prime Series Gen 2 Architecture](/content/trainingpdf/VER2-ARCH.pdf) - VER2-MMEDIA: [Developing Multimedia Solutions with Versal AI Edge and Prime Gen 2](/content/trainingpdf/VER2-MMEDIA.pdf) - VER-ARCH (formerly ACAP-VARCH): [Designing with the Versal Adaptive SoC Architecture](/content/trainingpdf/VER-ARCH.pdf) - VER-DEBUG (formerly ACAP-DEBUG): [Designing with the Versal Adaptive SoC Hardware Debug](/content/trainingpdf/VER-DEBUG.pdf) - VER-DM (formerly ACAP-VDM): [Designing with the Versal Adaptive SoC Design Methodology](/content/trainingpdf/VER-DM.pdf) - VER-MEM (formerly ACAP-MEM): [Designing with the Versal Adaptive SoC Memory Interfaces](/content/trainingpdf/VER-MEM.pdf) - VER-MGRT (formerly ACAP-MGRT): [Migrating from UltraScale+ Devices to Versal Adaptive SoCs](/content/trainingpdf/VER-MGRT.pdf) - VER-NOC (formerly ACAP-NOC): [Designing with the Versal Adaptive SoC Network on Chip](/content/trainingpdf/VER-NOC.pdf) - VER-PCIE (formerly ACAP-PCIE): [Designing with the Versal Adaptive SoC PCI Express Systems](/content/trainingpdf/VER-PCIE.pdf) - VER-PWR-BD (formerly ACAP-POWER-BD): [Designing with the Versal Adaptive SoC Power and Board Design](/content/trainingpdf/VER-PWR-BD.pdf) - VER-QSTART (formerly ACAP-QSTART): [Designing with the Versal Adaptive SoC Quick Start](/content/trainingpdf/VER-QSTART.pdf) - VER-TRX (formerly ACAP-TRX): [Designing with the Versal Adaptive SoC Serial Transceivers](/content/trainingpdf/VER-TRX.pdf) - VERSAL-101: [Getting Started with AMD's Versal Adaptive SoC](/content/trainingpdf/VERSAL-101.pdf)