# Accelerating Applications with the Vitis Unified Software Environment

## AI-ACCEL (v1.0) Course Specification

### Course Description
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center and embedded applications. The emphasis of this course is on:

- Using OpenCL™ APIs to run hardware kernels on Alveo™ accelerator cards
- Scheduling hardware kernels and controlling data movement by using OpenCL APIs and the Xilinx Runtime library for embedded platforms
- Demonstrating the Vitis environment GUI flow and makefile flow for both data center and embedded applications
- Optimizing designs

### What's New for 2023.1
- Analyzing reports with the Vitis analyzer tool
- Describing kernel development using C/C++ and RTL
- All labs have been updated to the latest software versions
- Vivado™ acceleration offers hardware designers a new mechanism for using Alveo boards

### Course Details
- 3 days instructor led training (online or in person)
- 24 lectures
- 12 labs
- Apply host code optimization and kernel optimization techniques
- Move data efficiently between kernel and global memory
- Profile the design using the Vitis analyzer tool
- Target Alveo accelerator cards with hardware-only designs

### Who Should Attend?
Anyone needing to accelerate software applications using FPGAs and adaptive SoCs (such as Zynq™ 7000, Zynq UltraScale+™, and Versal™ devices)

### Prerequisites
- Basic knowledge of AMD FPGA architecture
- Comfort with the C/C++ programming language (or equivalent training/experience)
- Familiarity with makefiles

### Course Outline
#### Day 1: Vitis Tool Flow
- Introduction to the Vitis Unified Software Platform
- Architecture: Alveo accelerator cards, SoCs, and ACAPs
- Demo board: Zynq UltraScale+ MPSoC ZCU104 board
- Vitis Unified Software Platform Overview for Accelerator Development

#### Day 2: Vitis Execution Model and XRT
- Describes the XRT and the OpenCL APIs used for setting up the system
- Xilinx Runtime Library (XRT) Native APIs
- Introduction to NDRanges
- Design Analysis: Profiling and Debugging

#### Day 3: Kernel Development
- Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators
- Optimization Methodology Guide
- Host Code Optimization and Platform Creation
- Vitis Accelerated Libraries

### Appendix
- Alveo Accelerator Card Ecosystem Partner Solutions (Optional)

### Student Cancellation Policy
- Student cancellations received more than 7 days before the first day of class are entitled to a 100% refund.
- Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.

## Images

Morgan Advanced Programmable Systems, Inc. (Morgan A.P.S.) delivers public and private courses in locations throughout the central US region; including Iowa, Illinois, Kansas, Minnesota, Missouri, Nebraska, North Dakota, South Dakota, and Wisconsin.

Website: morgan-aps.com/training for full course schedule and training information.