Designing with Versal AI Engine:

Architecture and Design Flow - 1

AIE-ARCH (v1.0)

Course Description

This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), and how to analyze a kernel program by using various debugger features. The emphasis of this course is on:

  • Describing the AI Engine (AIE) architecture
  • Illustrating the Versal AI Engine tool flow
  • Designing with single AI Engine kernels and analyzing the performance of scalar and vectorized kernels using the Vitis™ unified software platform
  • Describing the adaptive data flow graphs and designing with multiple AI Engine kernels with the Vitis Unified IDE
  • Analyzing and debugging kernel performance
  • Describing the AIE-ML architecture
  • Illustrating the programming model for the AIE-ML
  • Describing the AIE-ML v2 architecture for Versal AI Edge Series Gen 2 devices

What's New for 2025.2

  • AMD Versal AI Engine Tool Flow module: Added additional information on using the Vitis environment in the design flow
  • All labs have been updated to the latest software versions

Course Details

  • Duration: 2 days instructor led training (online or in person)
  • Level: VER 2
  • Course Part Number: AIE-ARCH
  • Who Should Attend? Software and hardware developers, system architects, and anyone who needs to accelerate their software applications using our devices

Prerequisites

  • Comfort with the C/C++ programming language
  • Describe the AMD Versal adaptive SoC architecture and the various compute domains at a high level and the motivation behind the AI Engine
  • Describe the architecture of the AI Engine
  • Enumerate the toolchain for Versal AI Engine programming and describe the full application acceleration flow with the AMD Vitis Unified IDE

Course Specification

  • Explain what AI Engine APIs are
  • Vitis application acceleration development flow

Software Tools

  • Vitis Unified IDE 2025.2

Hardware

  • Architecture: Versal adaptive SoCs
  • Program a single AI Engine kernel using scalar and vector data types using the Vitis tool
  • Program multiple AI Engine kernels using adaptive data flow (ADF) graphs
  • Analyze the performance and implementation reports of an AI Engine design using the Vitis Unified IDE
  • Describe the architecture of the AIE-ML
  • Describe the programming model for the AIE-ML

Course Outline

Day 1

Versal Adaptive SoC Architecture

Provides an overview of the Versal architecture at a high level and describes the various compute domains in the Versal device, such as the processor system, programmable logic, and AI Engines. Also describes how the AI Engine in the Versal device meets many dynamic market needs.

Versal AI Engine (AIE) Architecture

Introduces the architecture of the AI Engine and its components.

AI Engine Interfaces

Describes the AI Engine interfaces that are available, including the memory module architecture for the AI Engine and how memory can be accessed by the AI Engines in the AI Engine arrays.

Design Analysis

Covers the system design methodology and describes how Vitis Tool Flow provides an AI Engine functional overview and identifies the supported vector data types and high-width registers for allowing single-instruction multiple-data (SIMD) instructions.

AI Engine APIs

Describes what AI Engine APIs are, the three types of vector manipulation operations using AI Engine APIs (load and store, element conversion, and lane insertion/extraction), multiplication functions, and application-specific functions.

Buffers and Streaming Data APIs

Discusses the input/output buffers and streaming data APIs and reviews the various buffer operations for kernels.

The Programming Model: Single Kernel

Reviews the AI Engine kernel programming flow for programming and building a single kernel. Also illustrates the steps to create, compile, simulate, and debug a single kernel program using the Vitis Unified IDE.

Day 2

The Programming Model: Introduction to the Adaptive Data Flow (ADF) Graph

Provides the basics of the data flow graph model and graph input specifications for AI Engine programming. Also reviews graph input specifications, such as the number of platforms and ports.

The Programming Model: Multiple Kernels Using Graphs

Illustrates Versal AI Engine kernel programming in detail, reviewing the scalar kernel code and comparing it with vector kernel code that utilizes AI Engine APIs and vector data types.

Introduction to the AIE-ML Architecture

Introduces the architecture of the AIE-ML at different levels, such as the array, tiles, and components.

AIE-ML Memory Tiles and Programming

Describes the memory tiles in the AIE-ML architecture and illustrates AI Engine-ML programming using both shared buffers and external buffers with the AIE-ML.