Zynq UltraScale+ MPSoC for the Hardware Designer

EMBD-ZUPHW (v1.0)

Course Description

This course provides hardware designers with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC family from a hardware architectural perspective. The emphasis is on:

  • Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • Reviewing the various power domains and their control structure
  • Illustrating the processing system (PS) and programmable logic (PL) connectivity
  • Utilizing QEMU to emulate hardware behavior

What's New for 2025.2

  • Added lab - QEMU: Linux Application Development and Debugging
  • All labs have been updated to the latest software versions

Course Details

  • Duration: 2 days live instructor led training (online or in person)
  • Lectures: 30 lectures
  • Labs: 8 labs
  • Demos: 6 ILT demos / 1 On-Demand demo
  • Price: $1,600 or 16 AMD Training Credits
  • Course Part Number: EMBD-ZUPHW

Who Should Attend?

Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ MPSoC device.

Prerequisites

  • Suggested: Understanding of the Zynq 7000 architecture
  • Basic familiarity with embedded software development using C

Software Tools

  • Vivado™ Design Suite 2025.2
  • Vitis™ Unified IDE 2025.2
  • Hardware emulation environment:
    • VirtualBox (We use faster native installation)
    • QEMU (We use faster hardware)
    • Ubuntu desktop

After completing this comprehensive training, you will have the necessary skills to:

  • Enumerate the key elements of the application processing unit (APU)
  • Describe the connectivity between the processing system (PS) and programmable logic (PL)
  • List the various power domains and how they are controlled

Course Outline

Day 1

  • Application Processing Unit: Introduction to the members of the APU, specifically the Arm® Cortex®-A53 processor and how the cluster is configured and managed. {Lectures, Lab}

  • Real-Time Processing Unit: Focuses on the real-time processing (RPU) module in the PS, which is comprised of a pair of Cortex processors and supporting elements. {Lectures, Demo}

Day 2

  • QEMU: Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available. {Lectures, Demo, Labs}

  • Video: Introduction to video, video codecs, and the video codec unit available in the Zynq UltraScale MPSoC. {Lectures}

  • System Protection: Overview of clocking and reset, focusing more on capabilities than specific implementations. {Lectures, Demos}

  • AXI: Understanding how the PS and PL connect enables designers to create more efficient systems. {Lectures, Demo, Lab}

  • Power Management and the PMU: Overview of the PMU and the power-saving features of the device. {Lectures, Lab}

  • Debugging Using Cross-Triggering: Illustrates how HW-SW cross-triggering techniques can uncover issues. {Lecture, Lab}

Morgan Advanced Programmable Systems, Inc. (Morgan A.P.S.) delivers public and private courses in locations throughout the central US region; including Iowa, Illinois, Kansas, Minnesota, Missouri, Nebraska, North Dakota, South Dakota, and Wisconsin.