Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite

Course Description

This Morgan Advanced Programmable Systems, Inc., intensive custom course will train experienced FPGA designers to become fluent in Vivado Timing constraints and advanced features of Vivado. This course covers the fundamental timing scenarios encountered in a real-world FPGA design, and teaches which timing constraints to use for which scenario, why, and in some instances, discusses more than one way to properly constrain your design—all with the goal of making the engineering participants bring their designs to market faster with far fewer surprises. This course places a strong emphasis on writing maintainable and reviewable constraints using Tcl syntax in XDC files.

Reviewable constraints are preferred on real-world projects to allow other engineers to quickly see that the constraints are correct. Incorrect constraints are easy to write but will result in problems in the lab or once your product is in production.

Learning Objectives

  • Learn the underlying database and static timing analysis (STA) mechanisms.
  • Utilize Tcl for navigating the design, creating AMD design constraints (XDC), and creating timing reports.
  • Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.
  • Learn about path-specific, false path, and min/max timing constraints, as well as timing constraint precedence in the Vivado timing engine, and why it matters.
  • Learn about the scripting environment of the Vivado Design Suite and how to use the project-based scripting flow.
  • Acquire FPGA design best practices to improve design speed and reliability, including system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software.
  • Review the UltraFast design methodology checklist.

This course provides more labs and materials than can be covered in 3 days. Some of the more esoteric material will be left as an exercise for the reader, and the emphasis of this course is optimally constrained designs that build faster for a greater number of build iterations per day. This class focuses on a simple but unconstrained design with real-world timing scenarios, discussing the ideas behind the constraints as the design is constrained, as well as features of Vivado to quickly find and fix difficult timing paths.

Course Details

  • Course Duration: 3 days instructor-led training (online or in person)
  • Price: $2,700 or 27 AMD Training Credits
  • Course Part Number: FPGA-STAXDCADV

Prerequisites

  • Working knowledge of the VHDL or Verilog language
  • Digital design Experience

Level

  • FPGA 4

Hardware

  • Architecture: UltraScale™ FPGAs
  • Demo board: Zynq™ UltraScale+™ MPSoC ZCU104 board

Course Outline

Day 1

  • Static Timing Analysis and Metastability {Lecture}
  • Long Lab 1: System and source synchronous timing with readable/maintainable constraints.

Day 2

  • Clocking Wizard {Demo}
  • Constraint sets {Demo}
  • Create Clock using four methods {Demo}
  • Long lab/lecture continuation:

Day 3

  • Baselining {Lecture, Lab, Demo} (Optional)
  • Introduction to Timing Exceptions
  • Long lab/lecture continuation:

Course Specification

Course Specification
UltraFast Design Methodology: Design Closure Introduces the UltraFast™ design methodology guidelines covered in this course. {Lecture}
Scripting in Vivado Design Suite Non-Project Mode Write Tcl commands in the non-project batch flow for a design. {Lecture, Lab}
Hierarchical Design Overview of hierarchical design flows in the Vivado Design Suite. {Lecture}
Managing Remote IP Store IP and related files remote to the current working project directory. {Lecture, Lab}
I/O Timing Scenarios Overview of various I/O timing scenarios. {Lecture}
System-Synchronous I/O Timing Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface. {Lecture, Demo}
Source-Synchronous I/O Timing Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface. {Lecture, Lab}
Timing Constraints Priority Identify the priority of timing constraints. {Lecture}
Introduction to Floorplanning Introduction to floorplanning and how to use Pblocks. {Lecture}

Self-study

The following material and lab instructions are also provided to the student. Material not covered may be used for self-study (SS) or to refresh your memory on some of the techniques covered.

SS Day 1

  • Introduction to Clock Constraints – Apply clock constraints and perform timing analysis.
  • Generated Clocks – Use the report clock networks report to determine if there are any generated clocks in a design.
  • Report Clock Networks – Use report clock networks to view primary and generated clocks in a design.
  • Clock Group Constraints – Apply clock group constraints for asynchronous clock domains.

SS Day 2

  • Synchronization Circuits – Use synchronization circuits for clock domain crossings.
  • Report Datasheet – Use the datasheet report to find optimal setup and hold margin for an I/O interface.

SS Day 3

  • Overview of hierarchical design flows in the Vivado Design Suite. {Lecture}

SS Day 4

  • Understand the AMD bitstream security features such as readback disable, bitstream encryption, and authentication. {Lecture, Demo}
  • Vivado Design Suite Debug Methodology – Understand and follow debug core recommendations. {Lecture}.

This document is intended for informational purposes, summarizing the main content related to the Vivado STA, XDC, and Advanced Tools.