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Course Title

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  • ACAP-DEBUG * Designing with the Versal Adaptive SoC Hardware Debug
  • ACAP-MEM * Designing with the Versal Adaptive SoC Memory Interfaces
  • ACAP-MGRT * Migrating from UltraScale+ Devices to Versal Adaptive SoCs
  • ACAP-NOC * Designing with the Versal Adaptive SoC Network on Chip
  • ACAP-PCIE * Designing with the Versal Adaptive SoC PCI Express Systems
  • ACAP-POWER-BD * Designing with the Versal Adaptive SoC Power and Board Design
  • ACAP-QSTART * Designing with the Versal Adaptive SoC Quick Start
  • ACAP-TRX * Designing with the Versal Adaptive SoC Serial Transceivers
  • ACAP-VARCH * Designing with the Versal Adaptive SoC Architecture
  • ACAP-VDM * Designing with the Versal Adaptive SoC Design Methodology
  • AI-ACCEL * Accelerating Applications with the Vitis Unified Software Environment
  • AIE-ARCH * Designing with Versal AI Engine Architecture and Design Flow - 1
  • AIE-DSP * Designing with Versal AI Engine DSP Applications
  • AIE-GRAPH * Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2
  • AIE-KERNEL * Designing with Versal AI Engine Kernel Programming and Optimization - 3
  • AIE-QSTART * Designing with Versal AI Engine Quick Start
  • AI-INFER * Developing AI Inference Solutions with the Vitis AI Platform
  • CONN-PCIE * Designing an Integrated PCI Express System
  • CONN-RFSOC * Designing with the Zynq UltraScale+ RFSoC
  • DSP-HLS * High-Level Synthesis with the Vitis Unified IDE
  • DSP-MCSIM * Vitis Model Composer A MATLAB and Simulink-based Product
  • EMBD-88080 * Xilinx Rapid Development Embedded Design
  • EMBD-HET * Embedded Heterogeneous Design
  • EMBD-HW * Embedded Systems Design
  • EMBD-MMEDIA * Developing Multimedia Solutions Using a Hardened VCU-VDU
  • EMBD-PLNX * Embedded Design with PetaLinux Tools
  • EMBD-SW * Embedded Systems Software Design
  • EMBD-VITIS * Migrating to the Vitis Unified IDE
  • EMBD-ZSA * Zynq SoC System Architecture
  • EMBD-ZUPHW * Zynq UltraScale+ MPSoC for the Hardware Designer
  • EMBD-ZUPSA * Zynq UltraScale+ MPSoC for the System Architect
  • EMBD-ZUPSW * Zynq UltraScale+ MPSoC for the Software Developer
  • FPGA-DFX * Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite
  • FPGA-DSGNCLOSURE * Design Closure Techniques
  • FPGA-IPI * Designing with the IP Integrator Tool
  • FPGA-STAXDCADV * Vivado STA; XDC; and Advanced Tools and Techniques of Vivado Design Suite
  • FPGA-US * Designing with the UltraScale and UltraScale+ Architectures
  • FPGA-VDES1 * Designing FPGAs Using the Vivado Design Suite 1
  • FPGA-VDES2 * Designing FPGAs Using the Vivado Design Suite 2
  • FPGA-VDES3 * Designing FPGAs Using the Vivado Design Suite 3
  • FPGA-VDES4 * Designing FPGAs Using the Vivado Design Suite 4
  • FPGA-VDM * UltraFast Design Methodology
  • LANG-ADVVHDL * Advanced VHDL
  • LANG-SVDES * Designing with SystemVerilog
  • LANG-SVVER * Verification with SystemVerilog
  • LANG-VERILOG * Designing with Verilog
  • LANG-VHDL * Designing with VHDL
  • MPSOC-ACAP-SA * Adaptive SoCs for System Architects
  • MPSOC-BOOT-PM * Zynq UltraScale+ MPSoC Boot and Platform Management
  • SOC-OS-HYPER * Operating Systems and Hypervisors in Adaptive SoCs
  • SOM-ROBOTICS * Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS
  • SOM-VISION * Using Vision-based Applications with the Kria KV260 Vision AI
  • VERSAL-101 * Getting Started with AMD's Versal Adaptive SoC

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