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Start Days Course City State Register
06/02/2026 3 Accelerating Applications with the Vitis Unified Software Environment ( AI-ACCEL) Orono (Minneapolis) MN Full
06/02/2026 3 Accelerating Applications with the Vitis Unified Software Environment ( AI-ACCEL) Online Online Full
06/02/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Orono (Minneapolis) MN Closed
06/02/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Online Online Closed
06/02/2026 3 Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( FPGA-STAXDCADV) Orono (Minneapolis) MN Full
06/02/2026 3 Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( FPGA-STAXDCADV) Online Online Full
06/04/2026 2 Designing with Versal AI Engine Architecture and Design Flow - 1 ( AIE-ARCH) Schaumburg IL Closed
06/04/2026 2 Zynq UltraScale+ MPSoC for the Hardware Designer ( EMBD-ZUPHW) Schaumburg IL Closed
06/04/2026 2 Designing with the UltraScale and UltraScale+ Architectures ( FPGA-US) Schaumburg IL Closed
06/04/2026 2 Designing FPGAs Using the Vivado Design Suite 1 ( FPGA-VDES1) Orono (Minneapolis) MN Closed
06/04/2026 2 Designing FPGAs Using the Vivado Design Suite 1 ( FPGA-VDES1) Online Online Closed
06/04/2026 1 Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( SOM-ROBOTICS) Orono (Minneapolis) MN Closed
06/04/2026 1 Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( SOM-ROBOTICS) Online Online Closed
06/05/2026 1 Designing with Versal AI Engine DSP Applications ( AIE-DSP) Orono (Minneapolis) MN Full
06/05/2026 1 Designing with Versal AI Engine DSP Applications ( AIE-DSP) Online Online Full
06/05/2026 1 Migrating to the Vitis Unified IDE ( EMBD-VITIS) Orono (Minneapolis) MN Closed
06/05/2026 1 Migrating to the Vitis Unified IDE ( EMBD-VITIS) Online Online Closed
06/08/2026 2 Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( AIE-GRAPH) Orono (Minneapolis) MN Full
06/08/2026 2 Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( AIE-GRAPH) Online Online Full
06/08/2026 2 Design Closure Techniques ( FPGA-DSGNCLOSURE) Orono (Minneapolis) MN Closed
06/08/2026 2 Design Closure Techniques ( FPGA-DSGNCLOSURE) Online Online Closed
06/08/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Orono (Minneapolis) MN Closed
06/08/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Online Online Closed
06/09/2026 4 Xilinx Rapid Development Embedded Design ( EMBD-88080) Orono (Minneapolis) MN Full
06/09/2026 4 Xilinx Rapid Development Embedded Design ( EMBD-88080) Online Online Full
06/10/2026 1 Designing with Versal AI Engine Quick Start ( AIE-QSTART) Olathe KS Full
06/11/2026 2 Designing with Versal AI Engine Kernel Programming and Optimization - 3 ( AIE-KERNEL) Cedar Rapids IA Register
06/11/2026 2 Developing Multimedia Solutions Using a Hardened VCU-VDU ( EMBD-MMEDIA) Cedar Rapids IA Register
06/11/2026 2 Designing with the IP Integrator Tool ( FPGA-IPI) Orono (Minneapolis) MN Register
06/11/2026 2 Designing with the IP Integrator Tool ( FPGA-IPI) Online Online Register
06/11/2026 2 Designing FPGAs Using the Vivado Design Suite 3 ( FPGA-VDES3) Chicago IL Register
06/15/2026 3 Operating Systems and Hypervisors in Adaptive SoCs ( SOC-OS-HYPER) Chicago IL Register
06/15/2026 1 Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( SOM-ROBOTICS) Online Online Register
06/15/2026 1 Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( SOM-ROBOTICS) Naperville IL Register
06/15/2026 1 Designing with the Versal Adaptive SoC Serial Transceivers ( VER-TRX) Chicago IL Register
06/17/2026 2 Vitis Model Composer A MATLAB and Simulink-based Product ( DSP-MCSIM) Orono (Minneapolis) MN Register
06/17/2026 2 Vitis Model Composer A MATLAB and Simulink-based Product ( DSP-MCSIM) Online Online Register
06/17/2026 2 Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( FPGA-DFX) Orono (Minneapolis) MN Register
06/17/2026 2 Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( FPGA-DFX) Online Online Register
06/17/2026 3 Designing with Verilog ( LANG-VERILOG) Overland Park KS Register
06/17/2026 1 Designing with the Versal Adaptive SoC Quick Start ( VER-QSTART) Fargo ND Register
06/22/2026 2 Designing FPGAs Using the Vivado Design Suite 1 ( FPGA-VDES1) Orono (Minneapolis) MN Register
06/22/2026 2 Designing FPGAs Using the Vivado Design Suite 1 ( FPGA-VDES1) Online Online Register
06/22/2026 2 Zynq UltraScale+ MPSoC Boot and Platform Management ( MPSOC-BOOT-PM) Orono (Minneapolis) MN Register
06/22/2026 2 Zynq UltraScale+ MPSoC Boot and Platform Management ( MPSOC-BOOT-PM) Online Online Register
06/24/2026 3 Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( FPGA-STAXDCADV) Orono (Minneapolis) MN Register
06/24/2026 3 Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( FPGA-STAXDCADV) Online Online Register
06/24/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Orono (Minneapolis) MN Register
06/24/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Online Online Register
06/24/2026 3 Designing with VHDL ( LANG-VHDL) Orono (Minneapolis) MN Register
06/24/2026 3 Designing with VHDL ( LANG-VHDL) Online Online Register
06/25/2026 2 Embedded Heterogeneous Design ( EMBD-HET) Schaumburg IL Register
06/30/2026 2 Adaptive SoCs for System Architects ( ASOC-SA) Orono (Minneapolis) MN Register
06/30/2026 2 Adaptive SoCs for System Architects ( ASOC-SA) Online Online Register
06/30/2026 2 Using Vision-based Applications with the Kria KV260 Vision AI ( SOM-VISION) Schaumburg IL Register
06/30/2026 1 Designing with the Versal Adaptive SoC Serial Transceivers ( VER-TRX) Orono (Minneapolis) MN Register
06/30/2026 1 Designing with the Versal Adaptive SoC Serial Transceivers ( VER-TRX) Online Online Register
07/02/2026 2 Designing FPGAs Using the Vivado Design Suite 4 ( FPGA-VDES4) Orono (Minneapolis) MN Register
07/02/2026 2 Designing FPGAs Using the Vivado Design Suite 4 ( FPGA-VDES4) Online Online Register
07/03/2026 1 Designing with Versal AI Engine Quick Start ( AIE-QSTART) Orono (Minneapolis) MN Register
07/03/2026 1 Designing with Versal AI Engine Quick Start ( AIE-QSTART) Online Online Register
07/06/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Overland Park KS Register
07/06/2026 2 Zynq SoC System Architecture ( EMBD-ZSA) Overland Park KS Register
07/06/2026 2 Designing FPGAs Using the Vivado Design Suite 1 ( FPGA-VDES1) Overland Park KS Register
07/06/2026 2 Advanced VHDL ( LANG-ADVVHDL) Orono (Minneapolis) MN Register
07/06/2026 2 Advanced VHDL ( LANG-ADVVHDL) Online Online Register
07/06/2026 2 Designing with the Versal Adaptive SoC Memory Interfaces ( VER-MEM) Orono (Minneapolis) MN Register
07/06/2026 2 Designing with the Versal Adaptive SoC Memory Interfaces ( VER-MEM) Online Online Register
07/06/2026 2 Designing with the Versal Adaptive SoC Power and Board Design ( VER-MEM) Orono (Minneapolis) MN Register
07/06/2026 2 Designing with the Versal Adaptive SoC Power and Board Design ( VER-PWR-BD) Online Online Register
07/08/2026 2 Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( AIE-GRAPH) Orono (Minneapolis) MN Register
07/08/2026 2 Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( AIE-GRAPH) Online Online Register
07/08/2026 2 Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( FPGA-DFX) Schaumburg IL Register
07/08/2026 3 Designing with Verilog ( LANG-VERILOG) Orono (Minneapolis) MN Register
07/08/2026 3 Designing with Verilog ( LANG-VERILOG) Online Online Register
07/09/2026 2 Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( FPGA-DFX) Overland Park KS Register
07/09/2026 2 Designing with the Versal Adaptive SoC PCI Express Systems ( VER-PCIE) Orono (Minneapolis) MN Register
07/09/2026 2 Designing with the Versal Adaptive SoC PCI Express Systems ( VER-PCIE) Online Online Register
07/13/2026 2 Designing with Versal AI Engine Kernel Programming and Optimization - 3 ( AIE-KERNEL) Online Online Register
07/13/2026 2 Designing with Versal AI Engine Kernel Programming and Optimization - 3 ( AIE-KERNEL) Fargo ND Register
07/13/2026 2 Developing AI Inference Solutions with the Vitis AI Platform ( AI-INFER) Orono (Minneapolis) MN Register
07/13/2026 2 Developing AI Inference Solutions with the Vitis AI Platform ( AI-INFER) Online Online Register
07/13/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Naperville IL Register
07/13/2026 2 Embedded Systems Design ( EMBD-HW) Orono (Minneapolis) MN Register
07/13/2026 2 Embedded Systems Design ( EMBD-HW) Online Online Register
07/13/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Overland Park KS Register
07/13/2026 3 Designing with the Versal Adaptive SoC Design Methodology ( VER-DM) Hoffman Estates IL Register
07/14/2026 4 Xilinx Rapid Development Embedded Design ( EMBD-88080) Online Online Register
07/14/2026 4 Xilinx Rapid Development Embedded Design ( EMBD-88080) Olathe KS Register
07/15/2026 3 Accelerating Applications with the Vitis Unified Software Environment ( AI-ACCEL) Chicago IL Register
07/15/2026 2 Designing an Integrated PCI Express System ( CONN-PCIE) Chicago IL Register
07/15/2026 2 High-Level Synthesis with the Vitis Unified IDE ( DSP-HLS) Orono (Minneapolis) MN Register
07/15/2026 2 High-Level Synthesis with the Vitis Unified IDE ( DSP-HLS) Online Online Register
07/15/2026 3 Embedded Systems Software Design ( EMBD-SW) Schaumburg IL Register
07/15/2026 2 Designing with the Versal Adaptive SoC Architecture ( VER-ARCH) Orono (Minneapolis) MN Register
07/15/2026 2 Designing with the Versal Adaptive SoC Architecture ( VER-ARCH) Online Online Register
07/16/2026 2 UltraFast Design Methodology ( FPGA-VDM) Orono (Minneapolis) MN Register
07/16/2026 2 UltraFast Design Methodology ( FPGA-VDM) Online Online Register
07/16/2026 2 Verification with SystemVerilog ( LANG-SVVER) Schaumburg IL Register
07/20/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Orono (Minneapolis) MN Register
07/20/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Online Online Register
07/20/2026 2 Zynq UltraScale+ MPSoC for the Hardware Designer ( EMBD-ZUPHW) Orono (Minneapolis) MN Register
07/20/2026 2 Zynq UltraScale+ MPSoC for the Hardware Designer ( EMBD-ZUPHW) Online Online Register
07/20/2026 2 Designing with the Versal Adaptive SoC Architecture ( VER-ARCH) Schaumburg IL Register
07/20/2026 1 Designing with the Versal Adaptive SoC Network on Chip ( VER-NOC) Naperville IL Register
07/20/2026 2 Designing with the Versal Adaptive SoC Power and Board Design ( VER-PWR-BD) Naperville IL Register
07/21/2026 3 Designing with VHDL ( LANG-VHDL) Online Online Register
07/21/2026 3 Designing with VHDL ( LANG-VHDL) Olathe KS Register
07/22/2026 3 Accelerating Applications with the Vitis Unified Software Environment ( AI-ACCEL) Orono (Minneapolis) MN Register
07/22/2026 3 Accelerating Applications with the Vitis Unified Software Environment ( AI-ACCEL) Online Online Register
07/22/2026 3 Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( FPGA-STAXDCADV) Orono (Minneapolis) MN Register
07/22/2026 3 Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( FPGA-STAXDCADV) Online Online Register
07/23/2026 2 Zynq UltraScale+ MPSoC for the System Architect ( EMBD-ZUPSA) Champaign-Urbana IL Register
07/23/2026 2 Design Closure Techniques ( FPGA-DSGNCLOSURE) Orono (Minneapolis) MN Register
07/23/2026 2 Design Closure Techniques ( FPGA-DSGNCLOSURE) Online Online Register
07/23/2026 2 Designing with the IP Integrator Tool ( FPGA-IPI) Orono (Minneapolis) MN Register
07/23/2026 2 Designing with the IP Integrator Tool ( FPGA-IPI) Online Online Register
07/23/2026 2 Designing with SystemVerilog ( LANG-SVDES) Olathe KS Register
07/23/2026 2 Designing with the Versal Adaptive SoC Power and Board Design ( VER-PWR-BD) Champaign-Urbana IL Register
07/27/2026 2 Designing with Versal AI Engine Architecture and Design Flow - 1 ( AIE-ARCH) Online Online Register
07/27/2026 2 Designing with Versal AI Engine Architecture and Design Flow - 1 ( AIE-ARCH) Fargo ND Register
07/27/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Naperville IL Register
07/27/2026 2 High-Level Synthesis with the Vitis Unified IDE ( DSP-HLS) Orono (Minneapolis) MN Register
07/27/2026 2 High-Level Synthesis with the Vitis Unified IDE ( DSP-HLS) Online Online Register
07/27/2026 2 Embedded Heterogeneous Design ( EMBD-HET) Olathe KS Register
07/27/2026 1 Designing with the Versal Adaptive SoC Network on Chip ( VER-NOC) Saint Louis MO Register
07/27/2026 2 Designing with the Versal Adaptive SoC PCI Express Systems ( VER-PCIE) Orono (Minneapolis) MN Register
07/27/2026 2 Designing with the Versal Adaptive SoC PCI Express Systems ( VER-PCIE) Online Online Register
07/28/2026 2 Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( AIE-GRAPH) Fargo ND Register
07/29/2026 2 Adaptive SoCs for System Architects ( ASOC-SA) Overland Park KS Register
07/29/2026 2 Vitis Model Composer A MATLAB and Simulink-based Product ( DSP-MCSIM) Orono (Minneapolis) MN Register
07/29/2026 2 Vitis Model Composer A MATLAB and Simulink-based Product ( DSP-MCSIM) Online Online Register
07/29/2026 3 Designing with the Versal Adaptive SoC Design Methodology ( VER-DM) Orono (Minneapolis) MN Register
07/29/2026 3 Designing with the Versal Adaptive SoC Design Methodology ( VER-DM) Online Online Register
07/30/2026 2 Zynq UltraScale+ MPSoC for the Software Developer ( EMBD-ZUPSW) Olathe KS Register
07/30/2026 2 Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( FPGA-DFX) Naperville IL Register
08/03/2026 2 Developing Multimedia Solutions Using a Hardened VCU-VDU ( EMBD-MMEDIA) Overland Park KS Register
08/03/2026 3 Embedded Systems Software Design ( EMBD-SW) Olathe KS Register
08/05/2026 3 Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( FPGA-STAXDCADV) Schaumburg IL Register
08/05/2026 3 Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( FPGA-STAXDCADV) Online Online Register
08/06/2026 2 Designing FPGAs Using the Vivado Design Suite 1 ( FPGA-VDES1) Orono (Minneapolis) MN Register
08/06/2026 2 Designing FPGAs Using the Vivado Design Suite 1 ( FPGA-VDES1) Online Online Register
08/12/2026 2 Designing with Versal AI Engine Architecture and Design Flow - 1 ( AIE-ARCH) Orono (Minneapolis) MN Register
08/12/2026 2 Designing with Versal AI Engine Architecture and Design Flow - 1 ( AIE-ARCH) Online Online Register
08/12/2026 3 Designing with Verilog ( LANG-VERILOG) Orono (Minneapolis) MN Register
08/12/2026 3 Designing with Verilog ( LANG-VERILOG) Online Online Register
08/12/2026 2 Zynq UltraScale+ MPSoC Boot and Platform Management ( MPSOC-BOOT-PM) Orono (Minneapolis) MN Register
08/12/2026 2 Zynq UltraScale+ MPSoC Boot and Platform Management ( MPSOC-BOOT-PM) Online Online Register
08/13/2026 2 Developing AI Inference Solutions with the Vitis AI Platform ( AI-INFER) Chicago IL Register
08/13/2026 2 Designing an Integrated PCI Express System ( CONN-PCIE) Orono (Minneapolis) MN Register
08/13/2026 2 Designing an Integrated PCI Express System ( CONN-PCIE) Online Online Register
08/13/2026 2 Zynq SoC System Architecture ( EMBD-ZSA) Chicago IL Register
08/13/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Orono (Minneapolis) MN Register
08/13/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Online Online Register
08/17/2026 2 Embedded Design with PetaLinux Tools ( EMBD-PLNX) Orono (Minneapolis) MN Register
08/17/2026 2 Embedded Design with PetaLinux Tools ( EMBD-PLNX) Online Online Register
08/17/2026 1 Designing with the Versal Adaptive SoC Hardware Debug ( VER-DEBUG) Orono (Minneapolis) MN Register
08/17/2026 1 Designing with the Versal Adaptive SoC Hardware Debug ( VER-DEBUG) Online Online Register
08/17/2026 2 Designing with the Versal Adaptive SoC Power and Board Design ( VER-PWR-BD) Online Online Register
08/17/2026 2 Designing with the Versal Adaptive SoC Power and Board Design ( VER-PWR-BD) Fargo ND Register
08/18/2026 3 Accelerating Applications with the Vitis Unified Software Environment ( AI-ACCEL) Orono (Minneapolis) MN Register
08/18/2026 3 Accelerating Applications with the Vitis Unified Software Environment ( AI-ACCEL) Online Online Register
08/18/2026 4 Xilinx Rapid Development Embedded Design ( EMBD-88080) Orono (Minneapolis) MN Register
08/18/2026 4 Xilinx Rapid Development Embedded Design ( EMBD-88080) Online Online Register
08/18/2026 2 UltraFast Design Methodology ( FPGA-VDM) Orono (Minneapolis) MN Register
08/18/2026 2 UltraFast Design Methodology ( FPGA-VDM) Online Online Register
08/18/2026 1 Designing with the Versal Adaptive SoC Network on Chip ( VER-NOC) Saint Louis MO Register
08/19/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Orono (Minneapolis) MN Register
08/19/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Online Online Register
08/19/2026 2 Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( FPGA-DFX) Orono (Minneapolis) MN Register
08/19/2026 2 Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite ( FPGA-DFX) Online Online Register
08/19/2026 3 Designing with VHDL ( LANG-VHDL) Orono (Minneapolis) MN Register
08/19/2026 3 Designing with VHDL ( LANG-VHDL) Online Online Register
08/19/2026 1 Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( SOM-ROBOTICS) Orono (Minneapolis) MN Register
08/19/2026 1 Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS ( SOM-ROBOTICS) Online Online Register
08/20/2026 2 Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 ( AIE-GRAPH) Fargo ND Register
08/20/2026 2 Design Closure Techniques ( FPGA-DSGNCLOSURE) Orono (Minneapolis) MN Register
08/20/2026 2 Design Closure Techniques ( FPGA-DSGNCLOSURE) Online Online Register
08/20/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Orono (Minneapolis) MN Register
08/20/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Online Online Register
08/20/2026 2 Designing with the Versal Adaptive SoC Memory Interfaces ( VER-MEM) Overland Park KS Register
08/21/2026 1 Designing with Versal AI Engine DSP Applications ( AIE-DSP) Cedar Rapids IA Register
08/21/2026 1 Migrating to the Vitis Unified IDE ( EMBD-VITIS) Cedar Rapids IA Register
08/24/2026 2 Embedded Systems Design ( EMBD-HW) Online Online Register
08/24/2026 2 Embedded Systems Design ( EMBD-HW) Fargo ND Register
08/24/2026 2 Zynq UltraScale+ MPSoC for the System Architect ( EMBD-ZUPSA) Chicago IL Register
08/24/2026 2 Designing with the IP Integrator Tool ( FPGA-IPI) Orono (Minneapolis) MN Register
08/24/2026 2 Designing with the IP Integrator Tool ( FPGA-IPI) Online Online Register
08/24/2026 2 Advanced VHDL ( LANG-ADVVHDL) Orono (Minneapolis) MN Register
08/24/2026 2 Advanced VHDL ( LANG-ADVVHDL) Online Online Register
08/24/2026 1 Migrating from UltraScale+ Devices to Versal Adaptive SoCs ( VER-MGRT) Orono (Minneapolis) MN Register
08/24/2026 1 Migrating from UltraScale+ Devices to Versal Adaptive SoCs ( VER-MGRT) Online Online Register
08/24/2026 1 Designing with the Versal Adaptive SoC Network on Chip ( VER-NOC) Naperville IL Register
08/26/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Orono (Minneapolis) MN Register
08/26/2026 3 Designing with the Zynq UltraScale+ RFSoC ( CONN-RFSOC) Online Online Register
08/26/2026 3 Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( FPGA-STAXDCADV) Orono (Minneapolis) MN Register
08/26/2026 3 Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite ( FPGA-STAXDCADV) Online Online Register
08/31/2026 3 Accelerating Applications with the Vitis Unified Software Environment ( AI-ACCEL) Orono (Minneapolis) MN Register
08/31/2026 3 Accelerating Applications with the Vitis Unified Software Environment ( AI-ACCEL) Online Online Register
08/31/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Schaumburg IL Register
08/31/2026 2 Designing FPGAs Using the Vivado Design Suite 2 ( FPGA-VDES2) Online Online Register
08/31/2026 2 Designing FPGAs Using the Vivado Design Suite 3 ( FPGA-VDES3) Orono (Minneapolis) MN Register
08/31/2026 2 Designing FPGAs Using the Vivado Design Suite 3 ( FPGA-VDES3) Online Online Register
08/31/2026 2 Designing with SystemVerilog ( LANG-SVDES) Overland Park KS Register
08/31/2026 1 Designing with the Versal Adaptive SoC Hardware Debug ( VER-DEBUG) Saint Louis MO Register
08/31/2026 1 Designing with the Versal Adaptive SoC Quick Start ( VER-QSTART) Orono (Minneapolis) MN Register
08/31/2026 1 Designing with the Versal Adaptive SoC Quick Start ( VER-QSTART) Online Online Register
09/16/2026 1 Getting Started with AMD's Versal Adaptive SoC ( VERSAL-101) Online Online Register

Showing 1 to 208 of 208 entries

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